Applications abound for the use of high-speed transceivers, especially in the area of sensing and imaging. This circuitry typically involves driving and detecting sensors, which are often some type of infrared detector diode. The typical signals are very fast and require high-speed processes and wideband circuit design techniques.
LMI has recently completed development of a such a chipset. The function was split into separate transmitter and receiver ASICs, primarily to allow flexibility where multiple receivers are used for each transmitter, but this split has the ancillary benefit of keeping large, fast transmit signals away from the very sensitive receiver circuitry.
Initially a breadboard of the transceiver function using off-the-shelf discrete components and integrated circuits. This drove the development of initial target specifications for the transceiver from an input/output standpoint. LMI modified the discrete circuit architectures to best utilize a fully integrated approach.
An initial investigation was performed focusing on the key circuit blocks in the chip to determine how well the overall requirements could be met and to pick a target process. Based on this work, we decided to use a 180 nm SiGe BiCMOS process from Global Foundries. This process offered a good compromise between cost, both for masks and wafers, and performance. The fT of the medium voltage bipolar transistors is in the range 75 GHz nominally, which was determined to be sufficient for the customer’s requirements.
Once the specifications were finalized and the process chosen, we embarked on the detailed design. The transmitter had a few challenges but came together quite nicely. A number of programmable options were requested for this block which took some time to fully optimize. The receiver was significantly more challenging. First, the dynamic range of the receiver was quite large and required a very small noise floor. This put tough constraints onto the input trans-impedance amplifier (TIA). In addition, this TIA had to be stable and meet the noise current specifications over a range of detector capacitances, to maximize the flexibility of detector choice. The remainder of receive signal path was quite novel and was able to detect a wide input signal dynamic range with no external components. Both chips used an SPI interface with onboard RAM to store user programmability choices. The pinout and layout of both chips were very critical to the total system performance and a significant amount of care was given in this area.
Each chip is only 1.0 mm2 and are each packaged in a 3 mm x 3 mm, 24 lead QFN.