Chipmakers strictly implement verification and debugging in a typical analog and mixed signal SOC design. This is important for manufacturing companies to save billions of dollars effectively and efficiently.
The designs can have a huge impact on the verification cycle when they become bigger and more complex. In fact, verification engineers often face various challenges daily for the verification of modern mixed signal SOC.
What is a mixed signal SOC?
A mixed signal SOC is the integration of both analog and digital functionality within the same chip. The key in the verification process of the analog and mixed signal design is the interaction between them.
There can be various components within a semiconductor SOC at different levels of abstractions from different sources and languages. In the design process, there must be an integration of IPs at various levels without losing its overall design goals.
Thus, there should be a thorough testing of IP quality inside and outside of the SOC. Designers have a huge role during the design considering the size of SOC with multiple IPs. They must have effective debugging tools having quick and easy visualization, annotation, and navigation, among other tools to make the right decisions.
How do you debug a mixed signal SOC?
The cost of chips in the semiconductor industry is skyrocketing due to the global chip shortage, particularly in the automotive industry. The manufacture of a robust chip employs a long, iterative process that may require a lot of re-spins.
This is the main reason why it is very important to find and fix bugs as early as the development cycle than during the implementation wherein they can get a hundred times more expensive to fix.
As a result, proper verification and debugging will have fewer re-spins, faster market-to-market, lower costs, and more reliable products. But how do you debug a mixed signal SOC for that matter?
Here are steps to debug mixed signal SOC in an effective and efficient way to avoid certain issues:
- Test bench configuration using SPICE design and Verilog-AMS model in the AMS simulation
- Narrow down the issue in the SPICE design during the AMS simulation using the modeling approach
- Set up the correct Connect module via the Connect Rule in the AMS simulation
- Include the correct process corners in the SPICE simulation
- Force/access the SPICE net from the System Verilog test bench
- Speed up the simulation time using appropriate levels of wave dump in the SPICE simulation
- Select the appropriate simulator with the correct speed/accuracy options for the AMS simulations
- Use the Verilog-AMS netlist for the AMS simulations
Note that there are common issues encountered during the AMS simulation. AMS verification engineers can debug and verify mixed signal SOC using this guide.
- Pin swapped or mismatched between analog IPs when integrated at the analog top level
- Branch not terminated properly in a Verilog-AMS model
- The simulation takes longer due to the large dump file size and SPICE design
- Some domains do not show correct values because of incorrect connect module
- Improper simulator settings leading to incorrect results
- Mismatched digital control signals coming to the analog IPs
- Hierarchical references in the digital test bench
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