Challenges of Integrating Microprocessors and Memory in A System On a Chip (SOC)
Technological experts nowadays are relying more on integration, particularly in the field of microprocessors. However, there are challenges faced by engineers as it becomes harder to integrate system on a chip or SOC with the increasing amount of IP.
SOC integration has now been challenged with increased complexity such as multiple processors, power domains, and I/O. Here are several challenges that experts consider to be affecting technological advancement in different levels.
Problem with Complexity
Generally, people are not getting what they have expected. Expectations let them think that it is going to do something, but it does something else.
Another thing is complexity. Considerably, IP blocks are complicated, as well as the designs with such a short timeframe.
Timeframes Getting Too Short
Since integrators are under time pressure, it becomes quite challenging for integrators to do everything they can to achieve the highest quality in short period of time they have. At 15,000 CPUs running 24/7 for the verification process, it is a tough challenge.
Compatibility and Quality
Quality has a subjective and objective component. As far as the subjective component is concerned, nobody tends to get it right because it entirely depends on the user. On the objective component, however, it is what IP vendors are working to get right.
During the development of the system on a chip, sometimes the IP is being developed by other sources. Consequently, there will be more unknowns, while the other piece of verification is viewed at the IP level.
Moreover, it will be difficult to ensure that the specs are interpreted in the same way.
Challenges of Sharing System On a Chip Memory
The same issue about SOC designs in 1958 was addressed in recent years. This was the need for larger memories to cater to increasingly powerful SOC designs. But sharing memory presented several challenges.
- Shared memory physical interconnection
- Concurrent multiprocessor shared memory access
- Service-level guarantees
- System performance
Consequently, a design methodology has been developed to utilize the elements that will be able to address such challenges.
- Open-core protocol
- Sonics Graphical SOC design, test, and modeling tools
- MemMax memory access scheduler
- SiliconBackplane MicroNetwork
Such elements will provide designers with essential architectural features and shared memory operational visibility to achieve optimized system performance. The main architectural methodology has adopted the Local Area Network concepts that offer high-performance communication between heterogeneous entities using a translucent shared transport mechanism.
Solving the challenges of SOC shared memory might not be enough to cater to the needs of integrating microprocessors and memory on a system on a chip. Basically, it is just a design methodology that employs atomic split-transaction operations to support multiprocessing and exploit multi-threaded MicroNetwork interconnections and opportunistic external memory access optimizations.
Therefore, solving the shared memory challenges of SOC is just an outcome of methodology philosophy. Perhaps technological experts of today can take advantage of this opportunity that was used to solve the interconnections problem in 1958, using the SOC designs of today.
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